Architectural factors influencing the reliability of fault-tolerant VLSI arrays

Current trend in VLSI technology is toward highly modular structures in which identical Processing Elements (PE) are connected in a regular lattice. Enhancement of the operational reliability of these VLSI devices is obtained by means of fault-tolerance. Fault-tolerance is achieved incorporating spare PE's into the array and designing a flexible interconnection network which is able to support the reconfiguration of the array in the presence of a fault. This paper discusses how architectural related factors influence the configuration and the technology of the device, and how these factors can be accounted for in a predictive reliability model.