Abstract
We present the measurements of matching and high count rate performance of a 64 channel readout ASIC called DEDIX for high count rate position-sensitive measurements using semiconductor detectors. The ASIC is designed in 0.35 μm CMOS process and its total area is 3900 × 5000 μm2. The DEDIX has a binary readout architecture. Each channel is built of a charge sensitive amplifier (CSA) with a pole-zero cancellation circuit, a shaper, two independent discriminators and two independent 20-bit counters. The size of the input device in CSA has been optimized for a detector capacitance in the range of 1-3 pF per strip. An equivalent noise charge of 110 el rms has been achieved for a total detector capacitance of 1 pF at the shaper peaking time of 160 ns. Internal correction DAC implemented in each channel independently ensures a low spread of discriminator effective threshold, namely 0.4 mV at one sigma level. The mean gain in the multichannel ASIC is 54 μV/el, with a good uniformity from channel-to-channel (sd/mean ≈ 0.8%). Low noise performance and high rate capability have been demonstrated by the measurement up to and above 1 MHz average rate of input signals.
| Original language | English |
|---|---|
| Pages (from-to) | 1207-1215 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Nuclear Science |
| Volume | 54 |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - Aug 2007 |
Keywords
- Charge sensitive amplifier
- Count rate
- Matching
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