Architectural factors influencing the reliability of fault-tolerant VLSI arrays

Andrea Bobbio

doi:10.1016/0026-2714(91)90041-5

Architectural factors influencing the reliability of fault-tolerant VLSI arrays

Andrea Bobbio

Research output: Contribution to journal › Article › peer-review

Abstract

Current trend in VLSI technology is toward highly modular structures in which identical Processing Elements (PE) are connected in a regular lattice. Enhancement of the operational reliability of these VLSI devices is obtained by means of fault-tolerance. Fault-tolerance is achieved incorporating spare PE's into the array and designing a flexible interconnection network which is able to support the reconfiguration of the array in the presence of a fault. This paper discusses how architectural related factors influence the configuration and the technology of the device, and how these factors can be accounted for in a predictive reliability model.

Original language	English
Pages (from-to)	963-968
Number of pages	6
Journal	Microelectronics Reliability
Volume	31
Issue number	5
DOIs	https://doi.org/10.1016/0026-2714(91)90041-5
Publication status	Published - 1991
Externally published	Yes

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title = "Architectural factors influencing the reliability of fault-tolerant VLSI arrays",

abstract = "Current trend in VLSI technology is toward highly modular structures in which identical Processing Elements (PE) are connected in a regular lattice. Enhancement of the operational reliability of these VLSI devices is obtained by means of fault-tolerance. Fault-tolerance is achieved incorporating spare PE's into the array and designing a flexible interconnection network which is able to support the reconfiguration of the array in the presence of a fault. This paper discusses how architectural related factors influence the configuration and the technology of the device, and how these factors can be accounted for in a predictive reliability model.",

author = "Andrea Bobbio",

note = "Funding Information: {"}Work supported by the ItalianN ational Research Council CNR for Solid State Electronics{"},G rant 89.01857.61.",

year = "1991",

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language = "English",

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N1 - Funding Information: "Work supported by the ItalianN ational Research Council CNR for Solid State Electronics",G rant 89.01857.61.

PY - 1991

Y1 - 1991

N2 - Current trend in VLSI technology is toward highly modular structures in which identical Processing Elements (PE) are connected in a regular lattice. Enhancement of the operational reliability of these VLSI devices is obtained by means of fault-tolerance. Fault-tolerance is achieved incorporating spare PE's into the array and designing a flexible interconnection network which is able to support the reconfiguration of the array in the presence of a fault. This paper discusses how architectural related factors influence the configuration and the technology of the device, and how these factors can be accounted for in a predictive reliability model.

AB - Current trend in VLSI technology is toward highly modular structures in which identical Processing Elements (PE) are connected in a regular lattice. Enhancement of the operational reliability of these VLSI devices is obtained by means of fault-tolerance. Fault-tolerance is achieved incorporating spare PE's into the array and designing a flexible interconnection network which is able to support the reconfiguration of the array in the presence of a fault. This paper discusses how architectural related factors influence the configuration and the technology of the device, and how these factors can be accounted for in a predictive reliability model.

UR - https://www.scopus.com/pages/publications/0025767542

U2 - 10.1016/0026-2714(91)90041-5

DO - 10.1016/0026-2714(91)90041-5

M3 - Article

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SP - 963

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JO - Microelectronics Reliability

JF - Microelectronics Reliability

IS - 5

ER -

Architectural factors influencing the reliability of fault-tolerant VLSI arrays

Abstract

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